FIELD OF THE INVENTION
This invention relates to a latching circuit for sense amplifier in a DRAM (Dynamic RAM) and a DRAM utilizing the latching circuit, and more particularly, to a latching circuit for sense amplifier in a DRAM and a DRAM utilizing the latching circuit in which by decreasing the voltage level at the latching point of the latching circuit from the voltage level in its initial floating state to the voltage level which is lower than that of the bit line charging voltage, prior to being active of the latching control signal supplied to the latching circuit, a bit line sensing operation is enabled just after a latching control signal supplied to the latching circuit is active.